Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures

Abstract

Technology scaling has been one of the most fundamental ways to improve chip performance and reduce power consumption. However, as the industry dives deeper into the submicron regime, further scaling is encountering severe difficulties because the traditional MOSFET is facing atomistic and quantum-mechanical physics boundaries. It has become difficult to turn off the channel current due to short-channel effects (SCEs). This has led to the emergence of a 3D structure device, called FinFET. It has begun to replace traditional MOSFETs at 22nm and beyond due to its superior control over SCEs. This thesis explores the performance and power consumption of FinFET devices, from circuit to architecture level. It provides circuit designers with accurate FinFET models and simulators to evaluate their designs implemented with this new technology.

As power density increases, processor temperature problem arises. It becomes more severe under a manufacturing-time test environment in which power consumption is much higher than that in normal operation mode. We propose a thermal profiling framework for 2D and 3D FinFET circuits under the two most common testing scenarios, scan test and built-in self-test, as well as some of their low-power counterparts. We then compare results of those test methods and discuss the temperature impact.

Another urgent problem that needs to be addressed with continued technology scaling is how to analyze circuit performance and power consumption under process, voltage, and temperature (PVT) variations. Such variations arise due to limitations of lithography that lead to variations in the physical dimensions of the device or due to environmental variations. They can seriously impair the ratio of working chips among all chips fabricated, therefore reducing the profit. Besides accurate power and delay modeling for FinFET devices, this thesis also proposes statistical models to evaluate the power and delay deviations caused by PVT variations, taking into account spatial correlations. Based on the statistical models, it next presents GenFin, a multiobjective statistical FinFET logic circuit optimizer based on genetic algorithm (GA). It can simultaneously optimize timing, leakage power, and dynamic power yields through gate sizing. As opposed to traditional optimization tools that only provide one best solution, GenFin is able to produce a set of Pareto-optimal solutions to enable chip designers to make wise trade-offs. In the GenFin framework, we also propose an incremental timing analysis method as well as novel GA heuristics to speed up the analysis and optimization process.

We next discuss work on architectural modeling and analysis. Cache is one of the most important components of a processor. It occupies a large part of the chip and consumes a large portion of the total power. We present extensive results for caches composed of several types of FinFET SRAM cells and also study several low-power cache techniques. Then we introduce a design and simulation framework, called McPAT-PVT, for accurate and fast prediction of delay and power of FinFET-based processors under PVT variations. It supports various operation temperatures and frequencies, and can be applied to different processor configurations. We rigorously investigate area, delay, and power for various functional units and caches and also explore the timing and power yields of a FinFET processor based on the Alpha processor core. In addition, we present results for PARSEC real-traffic benchmarks for a chip multiprocessor architecture. Results show that processors implemented with asymmetric shorted-gate FinFET devices have the advantage of consuming far less power with little penalty in area or timing.