Please use this identifier to cite or link to this item:
http://arks.princeton.edu/ark:/88435/dsp01rr1720961
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Martonosi, Margaret | - |
dc.contributor.author | Mo, Vivian | - |
dc.date.accessioned | 2018-08-20T15:19:27Z | - |
dc.date.available | 2018-08-20T15:19:27Z | - |
dc.date.created | 2018-05-05 | - |
dc.date.issued | 2018-08-20 | - |
dc.identifier.uri | http://arks.princeton.edu/ark:/88435/dsp01rr1720961 | - |
dc.description.abstract | To increase performance, architectural heterogeneity is increasing which allows specialized components to operate more efficiently. These components often communicate through shared memory. Currently, memory consistency is difficult to reason about and implement without sacrificing performance in shared memory systems with heterogeneous components. This paper proposes a new memory consistency protocol, MemGlue, that enforces the C11 high-level language memory model to different architectural targets. MemGlue uses logical timestamps and network ordering to enforce heterogeneous consistency. By simulating MemGlue, we show that it is a hardware-efficient solution that can enforce heterogeneous memory consistency without significantly sacrificing performance in comparison to a traditional directory coherence protocol. | en_US |
dc.format.mimetype | application/pdf | - |
dc.language.iso | en | en_US |
dc.title | Simulation and Performance Analysis of the MemGlue Protocol | en_US |
dc.type | Princeton University Senior Theses | - |
pu.date.classyear | 2018 | en_US |
pu.department | Electrical Engineering | en_US |
pu.pdf.coverpage | SeniorThesisCoverPage | - |
pu.contributor.authorid | 960956543 | - |
Appears in Collections: | Electrical Engineering, 1932-2020 |
Files in This Item:
File | Description | Size | Format | |
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MO-VIVIAN-THESIS.pdf | 1.85 MB | Adobe PDF | Request a copy |
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