Power Modeling of Microprocessors via Emulation on a Field Programmable Gate Array

Abstract

The power dissipation of microprocessors has become an increasingly important issue in their design for reasons including energy efficiency and transistor performance. Designers often use modeling software to analyze the power characteristics of a processor before it is built because of the long time and effort required to construct physical hardware. These models can vary in level of detail, speed of computation, and accuracy, but are very reliant on the characteristics of ever-changing technology standards and often produce characteristics that are relatively accurate at best. On the other hand, Field Programmable Gate Arrays are designed to simulate various forms of hardware, and can be analyzed for power usage directly. This project will explore the possibility of modeling the power characteristics of microprocessors by simulating their power usage on an FPGA by continuing research from the previous semester.