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Please use this identifier to cite or link to this item: http://arks.princeton.edu/ark:/88435/dsp01hm50tv145
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dc.contributor.advisorVerma, Naveen-
dc.contributor.authorHuang, Liechao-
dc.contributor.otherElectrical Engineering Department-
dc.date.accessioned2016-06-08T18:43:02Z-
dc.date.available2016-06-08T18:43:02Z-
dc.date.issued2016-
dc.identifier.urihttp://arks.princeton.edu/ark:/88435/dsp01hm50tv145-
dc.description.abstractThrough five decades of Moore’s-law scaling, Integrated Circuits (ICs) have resulted in high- value functions, integrated with tremendous variety and capacity. Though excelling at computation, ICs have their drawbacks in interfacing with the physical world due to their form factor and limited ability to implement transducers (sensors, actuators, energy harvesters, etc.). On the other hand, by enabling diverse, flexible and large-scale transducers, Large-area Electronics (LAE) raises the potential for electronic systems to interact much more extensively with the physical world than is possible today. This can substantially expand the scope of applications, both in number and in value. But first, translation into applications requires a set of subsystem functions (instrumentation, computation, power management, communication, etc.). Though computational devices such as thin-film transistors can also be built in LAE, their low electrical performance tends to exclude them from realizing certain functions, such as computation and instrumentation. Thus it is necessary to combine LAE with high-performance, high-efficiency technologies, such as crystalline silicon CMOS ICs, within hybrid systems to leverage the advantages of both technologies. Such hybrid systems require: 1) rethinking each subsystem’s architecture from the start by considering how the functions should be allocated and how the technologies should be interfaced, on both a functional and physical level; and 2) developing new circuit topologies and algorithms for the whole hybrid architectures. In this thesis, we explore hybrid power management, wireless communication, sensing and instrumentation subsystems designed by employing new system architectures, circuit topologies, and specific algorithms. The top-down evaluation of design alternatives within the hybrid design space and pursuit of template architectures exposes circuit functions and device optimizations traditionally overlooked by bottom up approaches alone.-
dc.language.isoen-
dc.publisherPrinceton, NJ : Princeton University-
dc.relation.isformatofThe Mudd Manuscript Library retains one bound copy of each dissertation. Search for these copies in the library's main catalog: http://catalog.princeton.edu/-
dc.subjectAmorphous Silicon-
dc.subjectIntegrated Circuits-
dc.subjectLarge-area Electronics-
dc.subjectThin-film Transistor-
dc.subject.classificationElectrical engineering-
dc.subject.classificationComputer engineering-
dc.subject.classificationMaterials Science-
dc.titleLeveraging the Advantages of Large-Area Electronics and CMOS ICs in Hybrid Systems and Circuits-
dc.typeAcademic dissertations (Ph.D.)-
pu.projectgrantnumber690-2143-
Appears in Collections:Electrical Engineering

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