Exploring the system hierarchy from devices to on-chip communication

Abstract

FinFETs have replaced planar CMOS at and beyond the 22 nm node because of their superior short-channel behavior. Despite their significant advantages in electrostatics, FinFETs suffer from increased fringe capacitance because of the non-planar geometry. Parasitic capacitances affect the performance of numerous timing-critical circuits, such as voltage-controlled oscillator (VCO), content-adderessable memories (CAMs), and static random-access memories (SRAMs). Hence, accurate extraction of parasitic capacitances in FinFET and ultra-scaled CMOS circuits is an extremely important step in post-layout VLSI design flows and yet remains a very challenging task. Recently, technology computer-aided design (TCAD)-assisted automation in structure synthesis followed by a transport analysis-based capacitance extraction approach has shown a lot of potential in terms of accuracy and computational efficiency. However, extending TCAD from the circuit level to the array level still poses a major computational challenge. In the first three chapters of the thesis, we attempt to address this challenge, also known as the many-device TCAD barrier challenge. In the first work in this category, we present design possibilities of FinFET-based CAMs, aided by an accurate TCAD-assisted capacitance extraction methodology. For the first time, we explore the design space of FinFET CAMs and propose two capacitance-sensitive orthogonal layout styles for FinFET-based CAM design. In the second work in this category, we extend and validate the TCAD-assisted capacitance extraction methodology to extract parasitic capacitances that affect the oscillation frequency of a 10 GHz VCO. In the third work in this category, we extend the TCAD-assisted capacitance extraction framework to SRAM and logic arrays, proposing three methods to speed up capacitance extraction by partitioning the layout into several fragments.

The second emphasis of this thesis is on emerging monolithic 3D integration

technology and its applicability to FinFET SRAM design. Unlike the conventional

through-silicon-via (TSV)-based 3D integration methods, monolithic 3D integration

enables higher density of transistors owing to the much smaller monolithic inter-tier vias (MIVs). For the first time, we explore the design possibilities for several

FinFET-based ultra-high density monolithic 3D 6T and 8T SRAMs, taking detailed

process variations into account. We propose a new 8T 3D FinFET SRAM bitcell that

shows significant improvements in read stability and silicon footprint area without

affecting writeability, when compared with the conventional 2D 6T SRAM bitcell.

The third and final research direction of the thesis focuses on networks-on-chip

(NoCs). NoC is a type of communication architecture that addresses the scalability

problems of standard bus-based communication by distributing the communication

resources among the communicating components. Traditionally, analytical performance models have been used to speed up the extremely slow simulation/prototyping

phase of modern NoC design. However, the currently available analytical models’

outdatedness forces NoC designers to rely on simulation/prototyping. In view of this,

we propose a novel analytical NoC performance analysis methodology for modeling

the state-of-the-art single-cycle multi-hop asynchronous repeated traversal (SMART)

NoC that enables packets to partially or completely bypass routers from source to

destination. To the best of our knowledge, this is the first work on analytical modeling of NoCs that enable bypassing of routers.