Exploring Mixed-signal Computation for Energy Aggressive Interface Architectures

Abstract

Embedded sensor signals from an increasing variety of sources are enabling a broad range of intelligent systems. For instance, the systems aim to gain information about the state of the world, including its human inhabitants. However, the extraction of such information from embedded signals is challenging, since the signals naturally arise from complex physics of real-world processes. Machine-learning algorithms are addressing this challenge by enabling the construction of models for inferences from such complex signals, by using the data themselves. A key focus thus becomes the realization of such algorithms in highly energy-constrained sensing devices, despite the increasing compute complexity of the algorithms. In energy-constrained systems, a conventional way to resolve this problem is to employ application-specific circuits.

In this thesis, we have proposed using mixed-signal computation within unconventional architectures to overcome fundamental limitations that are faced in traditional digital application-specific architectures. But to maximize energy efficiency, the new architectures must avoid overheads typically incurred to correct mixed-signal circuit non-idealities. In order to maintain high overall system level performance, we also exploit the machine-learning approach of Data-Driven Hardware Resilience (DDHR), which involves statistical learning using data processed by the non-ideal circuits themselves, such that the machine-learning model optimally adapts to the non-idealities. This leads to substantial hardware-level relaxation and thus the potential for highly efficient system implementations.

To demonstrate our ideas, multiple hardware designs that are tested via silicon-CMOS prototypes are demonstrated. We first present a Time-domain Analog-to-Digital Converter (ADC) with Support Vector Machine (SVM) accelerator, to show the idea of DDHR in an embedded seizure detection system when overcoming analog non-idealities. Then, a SAR-ADC based matrix multiplier, referred to as the Matrix-Multiplying ADC (MMADC), is demonstrated as an example for mixed-signal computing. Then, an SRAM-based strong classifier (ClassRAM) is demonstrated. Further, system-level trade-offs and specialized algorithms are analyzed and developed, based on the in-memory architecture extended from ClassRAM, which enhance the application-level computational scalability of the architectures.