Discovering the Origin of Shallow Traps in Si-SiO\(_{2}\) Quantum Dots for Quantum Information Applications

Abstract

In the process of fabricating MOS quantum dots for quantum computing purposes, shallow traps in the conduction band that confine electrons have been observed at cryogenic temperatures. They are a major limitation in scaling solid state qubits, and there is much demand in understanding where they come from and how they can be eliminated. We hypothesize that the shallow traps originate from the slight grain-to-grain work function variations in the polycrystalline gate. If this is the case, using amorphous metal contacts which have much more uniform work functions should remove the shallow traps. In this work we set out to test this hypothesis with MOS devices using Ta\(_{40}\)W\(_{40}\)Si\(_{20}\) as our amorphous gate metal. Room temperature and 4.2 K \(I\)-\(V\) data of amorphous metal gate devices were characterized and a method of using our devices to probe the percolation threshold density is proposed. In the process it was discovered that performing a forming gas anneal of Al on TaWSi can effectively passivate Si-SiO\(_{2}\) interface defects.