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http://arks.princeton.edu/ark:/88435/dsp016969z281n| Title: | Logic Optimization for Binary Decoder Circuits - Simultaneous Area and Timing Optimization |
| Authors: | Tennant, Matthew |
| Advisors: | Malik, Sharad |
| Department: | Electrical Engineering |
| Class Year: | 1998 |
| Extent: | 23 Pages |
| Other Identifiers: | 9781 |
| URI: | http://arks.princeton.edu/ark:/88435/dsp016969z281n |
| Location : | This thesis can be viewed in person at the Mudd Manuscript Library. To order a copy complete the Senior Thesis Request Form. For more information contact mudd@princeton.edu. |
| Type of Material: | Princeton University Senior Theses |
| Appears in Collections: | Electrical Engineering, 1932-2020 |
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