Characterizing and Enhancing Energy Efficiency in Manycore Processors for Data Center Applications

Abstract

Power and energy have become primary design constraints for modern processors. Power no longer scales with transistor channel length, causing power density to increase. Continued transistor scaling will require prohibitively expensive cooling technologies. This is particularly an issue in data centers, where the cost of power and cooling has a major impact on the total cost of ownership. Data centers have grown and expanded rapidly due to the advent of cloud computing and interactive web services. The unabated migration of compute to data centers means future data centers will continue to require more compute which can be cooled in a cost-effective way. As a result, architects have looked to manycore processors due to their performance on parallel workloads and energy efficiency benefits. As opposed to conventional multicore data center processors which utilize a few large out-of-order cores optimized for instruction level parallelism, manycores utilize many smaller cores optimized for throughput. The sea of smaller cores work in parallel on a problem, each working on a smaller portion of the overall problem. As a result, each core can run slower, and the same amount of work can be completed in the same amount of time using less energy.

The focus of this thesis is to understand the power and energy characteristics of manycore processors and improve their already superior energy efficiency. Execution Drafting (ExecD) is a microarchitectural mechanism that exploits commonality between identical or similar programs or threads in data centers to improve the energy efficiency of fine-grained multithreaded cores. When similar or identical threads are scheduled to the same core, a thread synchronization mechanism that attempts to synchronize the threads in time to the same instruction takes over the thread scheduling decision. Once synchronized, identical instructions from different threads are consecutively issued down the pipeline, leading to reduced activity factors on control signals and potentially data buses resulting in energy savings. Additionally, if the threads are synchronized and their code is identical, the fetch stage can be disabled for all but one of the threads, resulting in a single instruction, multiple thread-like execution with increased energy efficiency. ExecD is evaluated with a custom-built simulator and in hardware based on the implementation in the Princeton Piton processor. Piton is a manycore research processor designed at Princeton which implements a tile-based architecture with on-chip networks for communication. It utilizes multithreaded cores and a distributed cache-coherent memory system for throughput and implements ExecD for energy efficiency. Piton was taped-out on IBM's 32nm SOI process and is fully functional, booting full-stack Debian Linux. This thesis details a full power and energy characterization of Piton, exploring many aspects of the processor. All data collected and the full hardware platform are open-source, providing a research platform for manycore processors and contributing valuable data to the research community. The power and energy data enable accurate high-level power modeling and insight into future manycore power and energy research. This thesis provides understanding of manycore processors from a power and energy perspective and demonstrates a viable technique for improving the energy efficiency of manycore processors in hardware.